1. INTRODUCTION:

The mini project is” PASSWORD ACCESS USING UART”. The main theme of this project is accessing the password in pc using uart.

In this project we used the keyboard to control the uart. With the use of this keyboard we can access password easily with press of single key.

Security is a prime concern in our day-today life. Everyone wants to be as much

secure as possible. An access control for doors forms a vital link in a security chain. The

password based access control system is a digital lock for doors that allows only authorized persons to access a restricted area. The system is fully controlled by the 16-bit ATMEGAmicrocontroller. The four digit password is stored in the ARRAY external to the ATMEGA16. The system has a keypad by which the password can be entered through it. When the entered password equals with the password stored in the memory then the relay gets on and so that the door is opened. If we entered a wrong password for more than five times then the alarm is switched on.

The user can type the password issued to him and if the entered password is correct

the LCD displays “Access Granted; Door is open”. An LED glow indicates that the relay

used for opening the door goes on. For an incorrect password entry, LCD displays “Invalid Password; Try Again !!!”. If the entered password is wrong for five consecutive trials, an alarm starts to sound. Now only a reset can make the system to the initial state.

At the time of each successful login, the currently entered password and time will be

sent to a PC through UART interface. The hyper terminal displays this and the same PC can be converted to a server data base for storing the log file.

In this project we used the keyboard to control the uart. With the use of this keyboard we can access password easily with press of single key.

The user can type the password issued to him and if the entered password is correct

the LCD displays “Access Granted; Door is open”. An LED glow indicates that the relay

2.COMPONENTS:

· Pc

· Programming cable

· At mega 16 l board

· AMS 1117 board

· UART board

· Resisters, capacitors

· Burk sheet pins

· Connecting wires

· 9 volts batteries

· Connecting wires

· Multi meter

3.UART

UniversalAsynchronousReceiver/Transmitter

UniversalAsynchronousReceiver/Transmitter (UART), to function properly. The UART chip takes the parallel output of the computer's system bus and transforms it into serial form for transmission through the serial port. In order to function faster, most UART chips have a built-in buffer of anywhere from 16 to 64 kilobytes. This buffer allows the chip to cache data coming in from the system bus while it is processing data going out to the serial port. While most standard serial ports have a maximum transfer rate of 115 Kbps (kilobits per second), high speed serial ports, such as Enhanced Serial Port (ESP) and Super Enhanced Serial Port (Super ESP), can reach data transfer rates of 460 Kbps.

3.1 UART interfacing

All computer operating systems in use today support serial ports, because serial ports have been around for decades. Parallel ports are a more recent invention and are much faster than serial ports. USB ports are only a few years old, and will likely replace both serial and parallel ports completely over the next several years.

The name "serial" comes from the fact that a serial port "serializes" data. That is, it takes a byte of data and transmits the 8 bits in the byte one at a time. The advantage is that a serial port needs only one wire to transmit the 8 bits (while a parallel port needs 8). The disadvantage is that it takes 8 times longer to transmit the data than it would if there were 8 wires. Serial ports lower cable costs and make cables smaller.

Before each byte of data, a serial port sends a start bit, which is a single bit with a value of 0. After each byte of data, it sends a stop bit to signal that the byte is complete. It may also send a parity bit.

Serial ports, also called communication (COM) ports, are bi-directional. Bi-directional communication allows each device to receive data as well as transmit it. Serial devices use different pins to receive and transmit data -- using the same pins would limit communication to half-duplex, meaning that information could only travel in one direction at a time. Using different pins allows for full-duplex communication, in which information can travel in both directions at once.

The Universal Asynchronous Receiver/Transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires.

Here we use max232 IC board .

The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the logic level signals of the UART to and from the external signaling levels. External signals may be of many different forms. Examples of standards for voltage signaling are and from the Historically, current was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such are IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are modulation of audio signals with phone line modems, RF modulation with data radios, and the DC-LIN for power line communication.

Communication may be "full duplex" (both send and receive at the same time) or "half duplex" (devices take turns transmitting and receiving).

Pronounced u-art, and short for universal asynchronous receiver-transmitter, the UART is a computer component that handles serasynchronousial communication. Every computer contains a UART to manage the serial ports, and some internal modems have their own UART.

As modems have become increasingly fast, the UART has come under greater scrutiny as the cause of transmission bottlenecks. If you are purchasing a fast external modem, make sure that the computer's UART can handle the modem's maximum transmission rate. The newer 16550 UART contains a 16-byte buffer, enabling it to support higher transmission rates than the older 8250 UART.

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (UART) is a Highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data Overrun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete

• Multi-processor Communication Mode• Double Speed Asynchronous Communication

3.2 AT mega 16:

Pin configurations

Figure 1. Pin out ATmega16

3.2.1 FEATURES:

• High-performance, Low-power AVR® 8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

_ On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 16K Bytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1K Byte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C (1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• High Endurance Non-volatile Memory segments

– 16K Bytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1K Byte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C (1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

3.2.2 PIN DESCRIPTION:

VCC Digital supply voltage.

GND Ground.

Port A (PA7...PA0) Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins\Can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B (PB7...PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ThePort B output buffers have symmetrical drive characteristics with both high sink and source Capability. As inputs, Port B pins that are externally pulled low will source current if the pull-upResistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C (PC7...PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source Capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up Resistors is activated. The Port C pins are tri-stated when a reset condition becomes active, Even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pinsPC5 (TDI), PC3 (TMS) and PC2 (TCK) will be activated even if a reset occurs. Port C also serves the functions of the JTAG interface and other special features of theATmega16 as listed.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source Capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up Resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, Even if the clock is not running.

Port D also serves the functions of various special features of the ATmega16 as listed.

RESET Input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected To VCC, even if the ADC is not used. If the ADC is used, it should.

3.2.3 AVR ATmega16 Memories:

This section describes the different memories in the ATmega16. The AVR architecture has two Main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

In-System

Reprogrammable

Flash Program

Memory

The ATmega16 contains 16K bytes On-chip In-System Reprogrammable Flash memory for program Storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8K x

16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16 Program Counter (PC) is 13 bits wide, thus addressing the 8K program memory locations. The Operation of Boot Program section and associated Boot Lock bits for software protection is Described in detail in “Boot Loader Support – Read-While-Write Self-Programming”. “Memory Programming” contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM

–“ Load Program Memory” Instruction Description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing”.

AREF: AREF is the analog reference pin for the A/D Converter. in Descriptions

VCC Digital supply voltage.3

Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pinscan provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, Even if the clock is not running.

Port B (PB7..PB0): Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source Capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up Resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, Even if the clock is not running.

Port B also serves the functions of various special features of the ATmega16 as listed.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5 (TDI), PC3 (TMS) and PC2 (TCK) will be activated even if a reset occurs. Port C also serves the functions of the JTAG interface and other special features of theATmega16 as listed

Port D also serves the functions of various special features of the ATmega16 as listed.

RESET Reset Input. A low level on this pin for longer than the minimum pulse length will generate Reset, even if the clock is not running. The minimum pulse length is given. Shorter pulses are not guaranteed to generate a reset.

3.2.4 ALTERNATE FUNCTIONS:

Port A

Port A has an alternate function as analog input for the ADC as shown. If some Port

Pins are configured as outputs, it is essential that these do not switch when a conversion is in Progress. This might corrupt the result of the conversion.

Relate the alternate functions of Port A to the overriding signals shown.

Alternate Functions of

Port B

The Port B pins with alternate functions are shown in below table

• SCK – Port B, Bit 7

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is Enabled as a Master, the data direction of this pin is controlled by DDB7. When the pin is forced By the SPI to be an input, the pull-up can still be controlled by the PORTB7 bit.

• MISO – Port B, Bit 6MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is Enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forcedby the SPI to be an input, the pull-up can still be controlled by the PORTB6 bit.

• MOSI – Port B, Bit 5

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is Enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.

• SS – Port B, Bit 4

SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input Regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is driven low.

When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB4. When The pin is forced by the SPI to be an input; the pull-up can still be controlled by the PORTB4 bit.

• AIN1/OC0 – Port B, Bit 3

AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up Switched off to avoid the digital port function from interfering with the function of the analog Comparator.

OC0, Output Compare Match output: The PB3 pin can serve as an external output for the

Timer/Counter0 Compare Match. The PB3 pin has to be configured as an output (DDB3 set (One)) To serve this function. The OC0 pin is also the output pin for the PWM mode timer Function.

• AIN0/INT2 – Port B, Bit 2:

AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up Switched off to avoid the digital port function from interfering with the function of the Analog Comparator.

INT2, External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to the MCU.

• T1 – Port B, Bit 1

T1, Timer/Counter1 Counter Source.

• T0/XCK – Port B, Bit 0

T0, Timer/Counter0 Counter Source.

XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is Output (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the USART operates In Synchronous mode.

Alternate Functions of

Port C

The Port C pins with alternate functions are shown. If the JTAG interface is enabled,

The pull-up resistors on pins PC5 (TDI), PC3 (TMS) and PC2 (TCK) will be activated even if a reset Occurs.

• TOSC2 – Port C, Bit 7

TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous Clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting Output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and The pin can not be used as an I/O pin.

• TOSC1 – Port C, Bit 6

TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous Clocking of Timer/Counter2, pin PC6 is disconnected from the port, and becomes the input of the Inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the Pin can not be used as an I/O pin.

• TDI – Port C, Bit 5

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TDO – Port C, Bit 4TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When The JTAG interface is enabled, this pin can not be used as an I/O pin. The TD0 pin is tri-stated unless TAP states that shifts out data are entered.

• TMS – Port C, Bit 3

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state Machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK – Port C, Bit 2

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• SDA – Port C, Bit 1

SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress Spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver With slew-rate limitation. When this pin is used by the Two-wire Serial Interface, the pull-up can Still be controlled by the PORTC1 bit.

• SCL – Port C, Bit 0

SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC0 is disconnected from the port and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress Spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver With slew-rate limitation. When this pin is used by the Two-wire Serial Interface, the pull-up can still be controlled by the PORTC0 bit.

• TMS – Port C, Bit 3

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state Machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin

• TCK – Port C, Bit 2

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• SDA – Port C, Bit 1

Alternate Functions of

Port D

• OC2 – Port D, Bit 7OC2, Timer/Counter2 Output Compare Match output: The PD7 pin can serve as an external output For the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDD7 Set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer Function.

• ICP1 – Port D, Bit 6

ICP1 – Input Capture Pin: The PD6 pin can act as an Input Capture pin for Timer/Counter1

• TXD – Port D, Bit 1

TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1.

• RXD – Port D, Bit 0RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this Pin is configured as an input regardless of the valueof DDD0. When the USART forces this pinto be an input, the pull-up can still be controlled by the PORTD0 bit.

3.3.1 UART – AVR USART vs. AVR Compatibility

The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Registers

• Baud Rate Generation

• Transmitter Operation

• Transmit Buffer Functionality

• Receiver Operation

However, the receive buffering have two improvements that will affect the compatibility in someSpecial cases:• A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More Important is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8) are Buffered with the data in the receive buffer. Therefore the status bits must always be read Before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost.

• The receiver Shift Register can now act as a third buffer level. This is done by allowing the Received data to remain in the serial Shift Register if the Buffer registers are

Full, until a new start bit is detected. The USART is therefore more resistant to Data Overrun (DOR) error conditions.

The following control bits have changed name, but have same functionality and register location:

• CHR9 is changed to UCSZ2• OR is changed to DOR

Clock Generation The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asynchronous,Master Synchronous and Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation.

Double Speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA

Pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (SlaveMode). The XCK pin is only active when using Synchronous mode

External Clock External clocking is used by the synchronous Slave modes of operation. The description in this Section refers to for details.

External clock input from the XCK pin is sampled by a synchronization register to minimize the

Chance of meta-stability. The output from the synchronization register must then pass through An edge detector before it can be used by the Transmitter and receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited

By the following equation:

Note that fuss depends on the stability of the system clock source. It is therefore recommended to

Add some margin to avoid possible loss of data due to frequency variations.

Clock Generation The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asynchronous, Master Synchronous and Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation.

Double Speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA

Pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (SlaveMode). The XCK pin is only active when using Synchronous mode

3.4 AMS 1117 IC:

GENERAL DESCRIPTION:

The AMS1117 series of adjustable and fixed voltage regulators are designed to provide 1A output current and to operate down to 1V input-to-output differential.

The dropout voltage of the device is guaranteed maximum 1.3V at maximum output current, decreasing at lower load currents.

On-chip trimming adjusts the reference voltage to 1%. Current limit is also trimmed, minimizing the stress under overload conditions on both the regulator and power source circuitry.

The AMS1117 devices are pin compatible with other three-terminal SCSI regulators and are offered in the low profile surface mount SOT-223 package, in the 8L SOIC package and in the TO-252 (DPAK) plastic package.

3.4.1 FEATURES APPLICATIONS

· Three Terminal Adjustable or Fixed Voltages*

1.5V, 1.8V, 2.5V, 2.85V, 3.3V and 5.0V

· Output Current of 1A

· Operates Down to 1V Dropout

· Line Regulation: 0.2% Max.

· Load Regulation: 0.4% Max.

· SOT-223, TO-252 and SO-8 package available

· Three Terminal Adjustable or Fixed Voltages*

1.5V, 1.8V, 2.5V, 2.85V, 3.3V and 5.0V

· Output Current of 1A

· Operates Down to 1V Dropout

· Line Regulation: 0.2% Max.

· Load Regulation: 0.4% Max.

· SOT-223, TO-252 and SO-8 package available

· Output Current of 1A

· Operates Down to 1V Dropout

· Line Regulation: 0.2% Max.

· Load Regulation: 0.4% Max.

· SOT-223, TO-252 and SO-8 package available

· Load Regulation: 0.4% Max.

· SOT-223, TO-252 and SO-8 package available

· Three Terminal Adjustable or Fixed Voltages*

1.5V, 1.8V, 2.5V, 2.85V, 3.3V and 5.0V

· Output Current of 1A

3.4.2 PIN CONNECTIONS:

3 PIN FIXED/ADJUSTABLE

VERSION

1- Ground/Adjust

2- VOUT

3- VIN

3.4.3 PIN DIAGRAM:

The AMS1117 series of adjustable and fixed voltage regulators are designed to provide 1A output current and to operate down to 1V input-to-output differential.

The dropout voltage of the device is guaranteed maximum 1.3V at maximum output current, decreasing at lower load currents.

On-chip trimming adjusts the reference voltage to 1%. Current limit is also trimmed, minimizing the stress under overload conditions on both the regulator and power source circuitry

The AMS1117 series of adjustable and fixed voltage regulators are designed to provide 1A output current and to operate down to 1V input-to-output differential.

The dropout voltage of the device is guaranteed maximum 1.3V at maximum output current, decreasing at lower load currents.

3.4.4 ASM1117 circuit diagram:

The AMS1117 series of adjustable and fixed regulators are easy.
To use and are protected against short circuit and thermal overloads. Thermal protection circuitry will shut-down the Regulator should the junction temperature exceed 165°C at the sense point.
Pin compatible with older three terminal adjustable regulators, these devices offer the advantage of a lower dropout voltage, more precise reference tolerance and improved reference stability.

The circuit design used in the AMS1117 series requires the use of an output capacitor as part of the device frequency compensation.

The addition of 22mF solid tantalum on the output will ensure stability for all operating conditions. When the adjustment terminal is bypassed with a capacitor to improve the ripple rejection, the requirement for an output capacitor increases.

The value of 22mF tantalum covers all cases of bypassing the adjustment terminal. Without bypassing the adjustment terminal smaller capacitors can be used with equally good results.

To further improve stability and transient response of these Devices larger values of output capacitor can be used.

The circuit design used in the AMS1117 series requires the use of an output capacitor as part of the device frequency compensation.

To further improve stability and transient response of these Devices larger values of output capacitor can be used.

3.4.5 Thermal Considerations

The AMS1117 series have internal power and thermal limiting Circuitry designed to protect the device under overload conditions.

However maximum junction temperature ratings of 125°C should not be exceeded under continuous normal load conditions.

Careful consideration must be given to all sources of thermal resistance from junction to ambient. For the surface mount package SOT-223 additional heat sources mounted near the device must be considered.

The heat dissipation capability of the PC board and its copper traces is used as a heat sink for the device. The thermal resistance from the junction to the tab for the AMS1117 is 15 ° C/W. Thermal resistances from tab to ambient can be as low as 30°C/W.

3.4.6 Ripple Rejection

The ripple rejection values are measured with the adjustment pin bypassed. The impedance of the adjust pin capacitor at the ripple frequency should be less than the value of R1 (normally100W to 200W) for a proper bypassing and ripple rejection approaching the values shown.

The size of the required adjust pin capacitor is a function of the input ripple frequency. If R1=100W at 120Hz the adjust pin capacitor should be >13mF. At 10 kHz only 0.16mF is needed.

The ripple rejection will be a function of output voltage, in circuits without an adjust pin bypass capacitor. The output ripple will increase directly as a ratio of the output voltage to the reference voltage (VOUT / VREF).

3.4.7 Protection Diodes:

Unlike older regulators, the AMS1117 family does not need any protection diodes between the adjustment pin and the output and from the output to the input to prevent over-stressing the die.

Internal resistors are limiting the internal current paths on the AMS1117 adjustment pin, therefore even with capacitors on the adjustment pin no protection diode is needed to ensure device safety under short-circuit conditions.

Diodes between the input and output are not usually needed. Microsecond surge currents of 50A to 100A can be handled by the internal diode between the input and output pins of the device.

In normal operations it is difficult to get those values of surge currents even with the use of large output capacitances. If high value output capacitors are used, such as 1000mF to 5000mF and the input pin is instantaneously shorted to ground, damage can occur However maximum junction temperature ratings of 125°C should not be exceeded under continuous normal load conditions.Careful consideration must be given to all sources of thermal resistance from junction to ambient. For the surface mount package SOT-223 additional heat sources mounted near the device must be considered.

A diode from output to input is recommended, when a crowbar circuit at the input of the AMS1117 is used (Figure 1).

3.4.8 Load Regulation:

True remote load sensing it is not possible to provide, because the AMS1117 is a three terminal device. The resistance of the wire connecting the regulator to the load will limit the load regulation.

The best load regulation is obtained when the top of the resistor divider R1 is connected directly to the case not to the load. If R1 were connected to the load, the effective resistance between the regulator and the load would be: RP x ( R2+R1 ) , RP = Parasitic Line Resistance.

The data sheet specification for load regulation is measured at the bottom of the package. Negative side sensing is a true Kelvin connection, with the bottom of the output divider returned to the negative side of the load, However maximum junction temperature ratings of 125°C should not be exceeded under continuous normal load conditions.Careful consideration must be given to all sources of thermal resistance from junction to ambient. For the surface mount package SOT-223 additional heat sources mounted near the device must be considered.

3.4.9 Output Voltage:

The AMS1117 series develops a 1.25V reference voltage between the output and the adjust terminal. Placing a resistor between these two terminals causes a constant current to flow through R1 and down through R2 to set the overall output voltage.

This current is normally the specified minimum load current of 10mA. Because IADJ is very small and constant it represents a small error and it can usually be ignored.

3.4.10 ABSOLUTE MAXIMUM RATINGS

Power Dissipation Internally limited

Input Voltage 15V

Power Transistor -40°C to 150°C

Control Section -40°C to 125°C

Storage temperature - 65°C to +150°C

Soldering information

Lead Temperature (10 sec) 300°C

SO-8 package j JA= 160°C/W

TO-252 package j JA= 80°C/W

SOT-223 package j JA= 90°C/W*

* With package soldering to copper area over backside

Ground plane or internal power plane j JA can vary from

46°C/W to >90°C/W depending on mounting technique and

The size of the copper area.

3.4.11 APPLICATION HINTS

The AMS1117 series of adjustable and fixed regulators are easyto use and are protected against short circuit and thermal Overloads.

Thermal protection circuitry will shut-down the regulator should the junction temperature exceed 165°C at the sense point. Pin compatible with older three terminal adjustable regulators, these devices offer the advantage of a lower dropout voltage, more precise reference tolerance and improved reference stability with temperature.

3.5MYKIT:

4. Operation:

Voltage source vc, vss are connect to the 9 volts, 5 volts pins.
Input 1, 2are connect to the port D1, D2 pins.
White, black pins of programming cable are connect to the 14, 15 pins of UART board.

Install the soft wares of PONYPROG 2000, HYPER TERMINAL
Open the programmer notepad and write the C program for controlling a motor.
Next click the make all to check the errors if there is no errors save the program.

Open the PONYPROG software click the main c file and store in to the ATMEGA 16 chips through the programming Take the ATMEGA16 board, UART board, programming cable, 9v batteries and connecting wires.
Give the connections of 9v battery to the ATMEGA 16 board.

Next remove the programming cable and connect the red color wire of programming cable to the ATMEGA 16 board.
Open the HYPER TERMINAL software and click the series option and press ok.

5. APPLICATIONS:

By using this project we can control any data carry device.
We can use this project in ATM.
We can also use this in cell phones devices.
This can be used in locking of doors in houses,schools etc.

6. CODING:

#include <avr/io.h>

#include "delay.h"

#include "lcd.h"

#include "uart.h"

void main ()

{

unsigned char x[5]={"akhil"},a[5];

unsigned char i,j,k;

lcd_init()

;

uartinit();

printstring ("\n enter your name");

for(i=0;i<=4;i++)

{

a[i]=dispdata();

printstring("*");

}

for(j=0;j<=4;j++)

{

if(a[j]==x[j])

{

k=1;

}

else

{

k=0;

}

if(k==1)

printstring("\n acess granted");

else

printstring("\n acess denied");

}

6. CONCLUSION:

The project”PASSWORD ACCESS USING UART” is successfully completed. In this project by using microcontroller, max232 IC(UART),programming cable,AMS1117(power supply board),PC battery .As we can dump the program to the microcontroller and give the instructions from the keyboard by using HYPERTERMINAL, after complication of the verification to the given input, if the password is correct it will be granted otherwise denied. By using this project we can control any data carry device and also We can use this project in ATM.

akhil's

Blog Archive

Sunday 7 August 2011

PASSWORD ACCESS USING UART

UniversalAsynchronousReceiver/Transmitter

3.2.2 PIN DESCRIPTION:

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